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FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports 96 kHz Sample Rates on Six Channels and 192 kHz on 2 Channels Supports 16-/20-/24-Bit Word Lengths Multibit Sigma-Delta Modulators with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs--Least Sensitive to Jitter Differential Output for Optimum Performance DACs Signal-to-Noise and Dynamic Range: 110 dB -94 dB THD + N--6-Channel Mode -95 dB THD + N--2-Channel Mode On-Chip Volume Control Per Channel with 1024-Step Linear Scale Software Controllable Clickless Mute Digital De-Emphasis Processing Supports 256 fS, 512 fS, and 768 fS Master Clock Modes Power-Down Mode Plus Soft Power-Down Mode Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible and DSP Serial Port Modes Supports Packed Data Mode (TDM) for DACs 48-Lead LQFP Plastic Package APPLICATIONS DVD Video and Audio Players Home Theatre Systems Automotive Audio Systems Set-Top Boxes Digital Audio Effects Processors
CDATA CLATCH CCLK MCLK RESET L/RCLK BCLK SDIN1 SDIN2 SDIN3 SOUT
Multichannel, 24-Bit, 192 kHz, - DAC AD1833
FUNCTIONAL BLOCK DIAGRAM
DVDD1 DVDD2 ZERO FLAGS AVDD OUTLP1 OUTLN1 OUTLP2 OUTLN2 OUTLP3 OUTLN3 OUTRP3 OUTRN3 OUTRP2 OUTRN2 OUTRP1 OUTRN1
SPI PORT
INTERPOLATOR
DAC
INTERPOLATOR
DAC
INTERPOLATOR
DAC
FILTER ENGINE
INTERPOLATOR
DAC
DATA PORT
INTERPOLATOR
DAC
INTERPOLATOR
DAC
AD1833
DGND FILTR FILTD AGND
The AD1833 is fully compatible with all known DVD formats, catering for up to 24-bit word lengths at sample rates of 48 kHz and 96 kHz on all six channels while supporting a 192 kHz sample rate on two channels. It also provides the "Redbook" standard 50 s/15 s digital de-emphasis filters at sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The AD1833 has a very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers, and sample rate converters. The AD1833 can be configured in left-justified, I2S, right-justified, or DSP serial port compatible modes. The AD1833 accepts serial audio data in MSB first, two's complement format. While the AD1833 can be operated from a single 5 V power supply, it also features a separate supply pin for its digital interface which allows the device to be interfaced to devices using 3.3 V power supplies. It is fabricated on a single monolithic integrated circuit and is housed in a 48-lead LQFP package for operation over the temperature range -40C to +85C.
GENERAL DESCRIPTION
The AD1833 is a complete, high-performance, single-chip, multichannel, digital audio playback system. It features six audio playback channels each comprising a high-performance digital interpolation filter, a multibit sigma-delta modulator featuring Analog Devices patented technology and a continuous-time voltage-out analog DAC section. Other features include an on-chip clickless attenuator and mute capability, per channel, programmed through an SPI-compatible serial control port.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD1833-SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance
5.0 V 25C 12.288 MHz, (256 x fS Mode) Nominally 1 kHz, 0 dBFS (Full Scale) 48 kHz 20 Hz to 20 kHz 24 Bits 500 pF 10 k
NOTES Performance of all channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice.
Parameter ANALOG PERFORMANCE DIGITAL-TO-ANALOG CONVERTERS Dynamic Range (20 Hz to 20 kHz, -60 dBFS Input) With A-Weighted Filter Total Harmonic Distortion + Noise
Min
Typ
Max
Unit
Test Conditions
106.5
SNR Interchannel Isolation DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Max Attenuation) Mute Attenuation De-Emphasis Gain Error Full-Scale Output Voltage at Each Pin (Single-Ended) Output Resistance Measured Differentially Common-Mode Output Volts DAC INTERPOLATION FILTER--48 kHz Pass Band Pass Band Ripple Stop Band Stop Band Attenuation Group Delay DAC INTERPOLATION FILTER--96 kHz Pass Band Pass Band Ripple Stop Band Stop Band Attenuation Group Delay DAC INTERPOLATION FILTER--192 kHz Pass Band Pass Band Ripple Stop Band Stop Band Attenuation Group Delay
110 110.5 -95 -94 -95 -94 110 108 3.0 0.2 80 -120 0.1 0.098 63.5 -120 0.1 1.0 (2.8) 150 2.2
-89
dB dB dB dB dB dB dB dB % % ppm/C dB Degrees % dB dB dB V rms (V p-p) V
fS = 96 kHz Two Channels Active Six Channels Active 96 kHz, Two Channels Active 96 kHz, Six Channels Active
20 0.01 24 70 510 37.7 0.03 55.034 70 160 89.954 1 104.85 70 140
kHz dB kHz dB s kHz dB kHz dB s kHz dB kHz dB s
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Parameter DIGITAL I/O Input Voltage HI Input Voltage LO Output Voltage HI Output Voltage LO POWER SUPPLIES Supply Voltage (AV DD and DVDD1) Supply Voltage (DVDD2) Supply Current I ANALOG Supply Current IDIGITAL Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins
Specifications subject to change without notice.
Min 3.0
Typ
Max
Unit V V V V V V mA mA mA dB dB
Test Conditions
0.8 DVDD2 - 0.4 0.4 4.5 3.3 5.0 38.5 42 2 -60 -50 5.5 DVDD1 42 45.5
Active Power-Down
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted)
AVDD, DVDDx to AGND, DGND . . . . . . . . -0.3 V to +6.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . -0.3 V to DVDD2 + 0.3 V Analog I/O Voltage to AGND . . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C
LQFP, JA Thermal Impedance . . . . . . . . . . . . . . . . . 91C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
ORDERING GUIDE
Model AD1833AST EVAL-AD1833EB
Temperature Range -40C to +85C
Package Description Thin Plastic Quad Flatpack Evaluation Board
Package Option ST-48
PIN CONFIGURATION
FILTR AGND OUTRP3 OUTRN3 OUTRP2 OUTRN2
36 35 34
OUTLN2
OUTLP2 OUTLN3
OUTLP3 AVDD
48 47 46 45 44 43 42 41 40 39 38 37
OUTLP1 1 OUTLN1 2 AVDD 3 AVDD 4 AGND 5 AGND 6 AGND 7 DGND 8 DVDD1 9 ZEROA 10 ZERO3R 11 ZERO3L 12
FILTD
PIN 1 IDENTIFIER
OUTRP1
AD1833
TOP VIEW (Not to Scale)
OUTRN1 AVDD 33 AVDD 32 AGND
31 30 29 28 27
AGND AGND DGND DVDD2
RESET ZERO1L 25 ZERO1R
26 13 14 15 16 17 18 19 20 21 22 23 24
ZERO2R CLATCH CDATA
BCLK MCLK SDIN1 SDIN2 SDIN3
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1833 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ZERO2L
CCLK L/RCLK
SOUT
WARNING!
ESD SENSITIVE DEVICE
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AD1833
DIGITAL TIMING (Guaranteed over -40 C to +85 C, AVDD = DVDD = 5.0 V 10%)
Min tDML tDMH tDBH tDBL tDLS tDLH tDDS tDDH tPDRP tCCH tCCL tCSU tCHD tCLH MCLK LO Pulsewidth (All Modes) MCLK HI Pulsewidth (All Modes) BCLK HI Pulsewidth BCLK LO Pulsewidth LRCLK Setup LRCLK Hold (DSP Serial Port Mode Only) SDATA Setup SDATA Hold PD/RST LO Pulsewidth CCLK HI Pulsewidth CCLK LO Pulsewidth CDATA Setup Time CDATA Hold Time CLATCH HI Pulsewidth 15 15 15 15 5 10 5 15 10 10 10 5 10 10
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications subject to change without notice.
tDMH
MCLK INPUT
tDML
RESET INPUT
tPDRP
Figure 1. MCLK and RESET Timing
tDBH
BCLK
tDBL tDLS
L/RCLK
SDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB-1
tDDH
SDATA I2S-JUSTIFIED MODE
tDDS
MSB
tDDH
SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 16-BIT CLOCKS (16-BIT DATA)
tDDS
MSB
tDDS
LSB
tDDH
tDDH
Figure 2. Serial Data Port Timing
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t CHD
CDATA D15 D14 D0
t CCH
CCLK
t CCL
CLATCH
t CSU t CLH
Figure 3. SPI Timing
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3, 4, 33, 34, 44 5, 6, 7, 30, 31, 32, 41 8, 29 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 35 36 37 38 39 40 42 43 45 46 47 48 REV. 0
Mnemonic OUTLP1 OUTLN1 AVDD AGND DGND DVDD1 ZEROA ZERO3R ZERO3L ZERO2R CLATCH CDATA CCLK L/RCLK BCLK MCLK SDIN1 SDIN2 SDIN3 SOUT ZERO2L ZERO1R ZERO1L RESET DVDD2 OUTRN1 OUTRP1 OUTRN2 OUTRP2 OUTRN3 OUTRP3 FILTR FILTD OUTLP3 OUTLN3 OUTLP2 OUTLN2
IN/OUT O O
Description DAC 1 Left Channel Positive Output. DAC 1 Left Channel Negative Output. Analog Supply. Analog Ground. Digital Ground. Digital Supply to Core Logic. Flag to Indicate Zero Input on All Channels. Flag to Indicate Zero Input on Channel 3 Right. Flag to Indicate Zero Input on Channel 3 Left. Flag to Indicate Zero Input on Channel 2 Right. Latch Input for Control Data (SPI Port). Serial Control Data Input (SPI Port). Clock Input for Control Data (SPI Port). Left/Right Clock for DAC Data Input (FSTDM Output in TDM Mode). Bit Clock for DAC Data Input (BCLKTDM Output in TDM Mode). Master Clock Input. Data Input for Channel 1 Left/Right (Data Stream Input in TDM and Packed Modes). Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary DAC in TDM Mode). Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary DAC in TDM Mode). Auxiliary I2S Output (Available in TDM Mode). Flag to Indicate Zero Input on Channel 2 Left. Flag to Indicate Zero Input on Channel 1 Right. Flag to Indicate Zero Input on Channel 1 Left. Power-Down and Reset Control. Power Supply to External Interface Logic. DAC 1 Right Channel Negative Output. DAC 1 Right Channel Positive Output. DAC 2 Right Channel Negative Output. DAC 2 Right Channel Positive Output. DAC 3 Right Channel Negative Output. DAC 3 Right Channel Positive Output. Reference/Filter Capacitor Connection. Recommend 10 F/100 F Decouple to Analog Ground. Filter Capacitor Connection. Recommend 10 F/100 F Decouple to Analog Ground. DAC 3 Left Channel Positive Output. DAC 3 Left Channel Negative Output. DAC 2 Left Channel Positive Output. DAC 2 Left Channel Negative Output. -5-
O O O O I I I I/O I/O I I I/O I/O O O O O I O O O O O O
O O O O
AD1833-Typical Performance Characteristics
0.01 0.008 0.006 0.004 0.002 0.1 0.08 0.06 0.04 0.02
dB
dB
0 -0.002 -0.004 -0.006 -0.008 -0.01 0 0.2 0.4 0.6 0.8 1.0 Hz 1.2 1.4 1.6 1.8 2.0 104
0 -0.02 -0.04 -0.06 -0.08 -0.1 0 0.5 1.0 1.5 Hz 2.0 2.5 3.0 3.5 104
TPC 1. Pass Band Response, 8 x Mode
TPC 4. Pass Band Response, 4 x Mode
10 0 -10 -20 -30
dB
0.5 0.4 0.3 0.2 0.1 dB 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.05 2.10 2.15 2.20 2.25 Hz 2.30 2.35 2.40 2.45 2.50 104 0 0.5 1.0 1.5 2.0 Hz 2.5 3.0 3.5 4.0 104
-40 -50 -60 -70 -80 -90 -100 2.00
TPC 2. Transition Band Response, 8 x Mode
TPC 5. 40 kHz Pass Band Response, 4 x Mode
10 0 -20 -40 -60 dB -80 -100 -120 -140 -160 0 0.5 1.0 1.5 Hz 2.0 2.5 3.0 105 0 -10 -20 -30
dB
-40 -50 -60 -70 -80 -90 -100 4.0 4.2 4.4 4.6 4.8 5.0 Hz 5.2 5.4 5.6 5.8 6.0 104
TPC 3. Complete Response, 8 x Mode
TPC 6. Transition Band Response, 4 x Mode
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AD1833
10
0 -20 -40 -60
0 -10 -20 -30
dB
-80 -100 -120
dB
0 0.5 1.0 1.5 Hz 2.0 2.5 3.0 105
-40 -50 -60 -70 -80
-140 -160
-90 -100 0.80 0.85 0.90 0.95 1.00 Hz 1.05 1.10 1.15 1.20 105
TPC 7. Complete Response, 4 x Mode
TPC 9. Transition Band Response, 2 x Mode
2.0
0
1.5
-20
1.0 0.5
dB
-40 -60 dB -80 -100 -120 -140 -160
0 -0.5 -1.0 -1.5 -2.0 0 1 2 3 4 Hz 5 6 7 8 104
0
0.5
1.0 Hz
1.5
2.0 105
TPC 8. 80 kHz Pass Band Response, 2 x Mode
TPC 10. Complete Response, 2 x Mode
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AD1833
FUNCTIONAL DESCRIPTION Device Architecture
The modulator samples the output of the interpolator stage(s) at a rate of 6.144 MHz.
OPERATING FEATURES SPI Register Definitions
The AD1833 is a 6-channel audio DAC featuring multibit Sigma-Delta (-) technology. The AD1833 features three stereo converters (giving six channels) where each stereo channel is controlled by a common bit-clock (BCLK) and synchronization signal (L/RCLK).
Interpolator
The interpolator consists of up to three stages of sample rate doubling and half-band filtering followed by a 16 sample zero order hold. The sample rate doubling is achieved by zero stuffing the input samples, and a digital half band filter is then used to remove any images above the band of interest and to bring the zero samples to their correct values. By selecting different input sample rates, one, two, or all three stages of doubling may be switched in. This allows for three different sample rate inputs. All three doubling stages are used with the 48 kHz input sample rate, with the 96 kHz input sample rate only two doubling stages are used, and with the 192 kHz input sample rate only one doubling stage is used. In each case the input sample frequency is increased to 384 kHz. The ZeroOrder Hold (ZOH) holds the interpolator samples for upsampling by the modulator. This is done at a rate 16 times the interpolator output sample rate.
Modulator
The SPI port allows flexible control of the devices' programmable functions. It is organized around nine registers; six individual channel VOLUME registers and three CONTROL registers. Each WRITE operation to the AD1833 SPI control port requires 16 bits of serial data in MSB-first format. The four most significant bits are used to select one of nine registers (seven register addresses are reserved), and the bottom 10 bits are then written to that register. This allows a write to one of the nine registers in a single 16-bit transaction. The SPI CCLK signal is used to clock in the data. The incoming data should change on the falling edge of this signal and remain valid during the rising edge. At the end of the 16 CCLK periods, the CLATCH signal should rise to latch the data internally into the AD1833. See Figure 2. The serial interface format used on the Control Port utilizes a 16-bit serial word as shown in Table I. The 16-bit word is divided into several fields: Bits 15-12 define the register address, Bits 11 and 10 are reserved and must be programmed to 0, and Bits 9-0 are the data field (which has specific definitions, depending on the register selected).
The modulator is a 6-bit, second-order implementation and uses data scrambling techniques to achieve perfect linearity.
Table I. Control Port Map
Register Address 15
2
Reserved1 12 11 10 9 8 7 6
Data Field 5 4 3 2 1 0
14
13
NOTES 1 Must be programmed to zero. 2 Bit 15 = MSB
Bit 15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 14 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bit 13 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Bit 12 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Register Function DAC Control I DAC Control II DAC Volume 1 DAC Volume 2 DAC Volume 3 DAC Volume 4 DAC Volume 5 DAC Volume 6 DAC Control III Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Table II. DAC Control I Function Data Word Width Power-Down RESET Interpolator Mode
Address
Reserved*
De-Emphasis
Serial Mode
15-12 0000
11 0
10 0
9-8 00 = None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz
7-5 000 = I S 001 = RJ 010 = DSP 011 = LJ 100 = Pack Mode 1 (256) 101 = Pack Mode 2 (128) 110 = AUX Mode 111 = Reserved
2
4-3
2
1-0 00 = 8x (48 kHz) 01 = 2x (192 kHz) 10 = 4x (96 kHz) 11 = Reserved
00 = 24 Bits 0 = Normal 01 = 20 Bits 1 = PWRDWN 10 = 16 Bits 11 = Reserved
*Must be programmed to zero.
DAC CONTROL REGISTER I De-Emphasis
DAC Word Width
The AD1833 has a built-in de-emphasis filter that can be used to decode CDs that have been encoded with the standard "Redbook" 50 s/15 s emphasis response curve. Three curves are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sampling rates. The filters may be selected by writing to Control Bits 9 and 8 in DAC Control Register I, see Table III.
Table III. De-Emphasis Settings
The AD1833 will accept input data in three separate wordlengths--16, 20, and 24 bits. The word-length may be selected by writing to Control Bits 4 and 3 in DAC Control Register I, see Table V.
Table V. Word Length Settings
Bit 4 0 0 1 1
Power-Down Control
Bit 3 0 1 0 1
Word Length 24 Bits 20 Bits 16 Bits Reserved
Bit 9 0 0 1 1
Bit 8 0 1 0 1
De-Emphasis Disabled 44.1 kHz 32 kHz 48 kHz
Data Serial Interface Mode
The AD1833's serial data interface is designed to accept data in a wide range of popular formats including I2S, right justified (RJ), left justified (LJ) and flexible DSP modes. The L/RCLK pin acts as the word clock (or Frame Sync) to indicate sample interval boundaries. The BCLK defines the serial data rate while the data is input on the SDIN1-3 pins. The serial mode settings may be selected by writing to Control Bits 7 through 5 in DAC Control Register I, see Table IV.
Table IV. Data Serial Interface Mode Settings
The AD1833 can be powered down by writing to Control Bit 2 in DAC Control Register I, see Table VI. The power-down/ reset bit is not latched when the CLATCH is brought high to latch the entire word, but only after the following low-to-high CLATCH transition. Therefore, to put the part in power-down, or to bring it back up from power-down, the command should be written twice.
Table VI. Power-Down Control
Bit 2 0 1
Interpolator Mode
Power-Down Setting Normal Operation Power-Down Mode
Bit 7 0 0 0 0 1 1 1 1
Bit 6 0 0 1 1 0 0 1 1
Bit 5 0 1 0 1 0 1 0 1
Serial Mode I2 S Right Justify DSP Left Justify Packed Mode 1 (256) Packed Mode 2 (128) AUX Mode Reserved
The AD1833's DAC interpolators can be operated in one of three modes--8x, 4x, or 2x corresponding with 48 kHz, 96 kHz, and 192 kHz modes respectively. The Interpolator Mode may be selected by writing to Control Bits 1 and 0 in DAC Control Register I, see Table VII.
Table VII. Interpolator Mode Settings
Bit 1 0 0 1 1
Bit 0 0 1 0 1
Interpolator Mode 8x (48 kHz) 2x (192 kHz) 4x (96 kHz) Reserved
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Table VIII. DAC Control II
Function Address 15-12 0001 Reserved* 11 0 10 0 Reserved* 9-6 0 5 Channel 6 0 = Mute Off 1 = Mute On 4 3 Mute Control 2 Channel 3 0 = Mute Off 1 = Mute On 1 0
Channel 5 Channel 4 0 = Mute Off 0 = Mute Off 1 = Mute On 1 = Mute On
Channel 2 Channel 1 0 = Mute Off 0 = Mute Off 1 = Mute On 1 = Mute On
*Must be programmed to zero.
DAC CONTROL REGISTER II
DAC Control Register II contains individual channel mute controls for each of the 6 DACs. Default operation (bit = 0) is muting off. Bits 9 through 6 of Control Register II are reserved and should be programmed to zero, see Table VIII.
Table IX. Muting Control
DAC CONTROL REGISTER III Stereo Replicate
Bit 5 X X X X X 1
Bit 4 X X X X 1 X
Bit 3 X X X 1 X X
Bit 2 X X 1 X X X
Bit 1 X 1 X X X X
Bit 0 1 X X X X X
Muting Mute Channel 1 Mute Channel 2 Mute Channel 3 Mute Channel 4 Mute Channel 5 Mute Channel 6
The AD1833 allows the stereo information on Channel 1 (SDIN1--Left 1 and Right 1) to be copied to Channels 2 and 3 (Left/Right 2 and Left/Right 3). These signals can be used in an external summing amplifier to increase potential signal SNR. Stereo Replicate mode can be enabled by writing to Control Bit 5, see Table XI. Note that replication is not reflected in the zero flag status.
Table XI. Stereo Replicate
Bit 5 0 1
Stereo Mode Normal Channel 1 Data Replicated on Channels 2 and 3
Table X. DAC Control III Function Address 15-12 1000
Reserved*
Reserved* 9-6 0
Stereo Replicate (192 kHz) 5 0 = Normal 1 = Replicate
MCLK Select 4-3 00 = 256 x fS (MCLK x 2) 01 = 512 x fS (MCLK Straight Through) 10 = 768 x fS (MCLK x 2/3)
Zero Detect 2 0 = Active High 1 = Active Low
Reserved 1-0
11 0
10 0
*Must be programmed to zero.
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AD1833
MCLK Select
The AD1833 allows the matching of available external MCLK frequencies to the required sample rate. The oversampling rate can be selected from 256 x fS, 512 x fS or 768 x fS by writing to Bit 4 and Bit 3. Internally the AD1833 requires an MCLK of 512 x fS; therefore, in the case of 256 x fS mode, a clock doubler is used, whereas in 768 x fS mode, a divide-by-3 block (/3) is first implemented, followed by a clock doubler. See Table XII.
Table XII. MCLK Settings
is programmable by writing to Control Bit 2, see Table XIII. The six individual channel flags are best used as three stereo zero flags by combining pairs of them through suitable logic gates. Then, when both the left and right input are zero for 1024 clock cycles, i.e., a stereo zero input for 1024 sample periods, the combined result of the two individual flags will go active indicating a stereo zero.
Table XIII. Zero Detect
Bit 2 0 1
Channel Zero Status Active High Active Low
Bit 4 0 0 1 1
Bit 3 0 1 0 1
Oversample Ratio 256 x fS (MCLK x 2 Internally) 512 x fS 768 x fS (MCLK x 2/3 Internally) Reserved
DAC Volume Control Registers
Channel Zero Status
The AD1833 provides individual logic output status indicators when zero data is sent to a channel for 1024 or more consecutive sample periods. There is also a global zero flag that indicates all channels contain zero data. The polarity of the active zero signal
The AD1833 has six volume control registers, one each for the six DAC channels. Volume control is exercised by writing to the relevant register associated with each DAC. This setting is used to attenuate the DAC output. Full-scale setting (all 1s) is equivalent to zero attenuation. See Table XV.
Table XIV. MCLK vs. Sample Rate Selection
MCLK (MHz) Sampling Rate fS (kHz) 32 64 128 44.1 88.2 176.4 48 96 192 Interpolator Mode 8x (Normal) 4x (Double) 2x (4 Times) 8x (Normal) 4x (Double) 2x (4 Times) 8x (Normal) 4x (Double) 2x (4 Times) 256 fS 8.192 512 fS 16.384 768 fS 24.576
11.2896
22.5792
33.8688
12.288
24.576
36.864
Table XV. Volume Control Registers
Address 15-12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1
Reserved* 11 0 10 0
Volume Control 9-0 Channel 1 Volume Control (OUTL1) Channel 2 Volume Control (OUTR1) Channel 3 Volume Control (OUTL2) Channel 4 Volume Control (OUTR2) Channel 5 Volume Control (OUTL3) Channel 6 Volume Control (OUTR3)
*Must be programmed to zero.
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AD1833
I2S Timing
I2S timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is low for the left channel and high for the right channel. A bit clock running at 64 x fS is used to clock in the
L/RCLK INPUT BCLK INPUT SDATA INPUT
MSB -1 MSB -2 LSB +2 LSB +1
data. There is a delay of one bit clock from the time the L/RCLK signal changes state to the first bit of data on the SDINx lines. The data is written MSB first and is valid on the rising edge of bit clock.
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
MSB MSB -1 -2
LSB +2
LSB +1
LSB
MSB
Figure 4. I 2S Timing Diagram
Left Justified Timing
Left Justified (LJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is high for the left channel and
L/RCLK INPUT
low for the right channel. A bit clock running at 64 x fS is used to clock in the data. The first bit of data appears on the SDINx lines at the same time the L/RCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock.
LEFT CHANNEL
RIGHT CHANNEL
BCLK INPUT SDATA INPUT
MSB -1 MSB -2 LSB +2 LSB +1 MSB -1 MSB -2 LSB +2 LSB +1 MSB -1
MSB
LSB
MSB
LSB
MSB
Figure 5. Left-Justified Timing Diagram
Right Justified Timing
Right Justified (RJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is high for the left channel and low for the right channel. A bit clock running at 64 x fS is used
L/RCLK INPUT BCLK INPUT SDATA INPUT
MSB -1 MSB -2 LSB +2 LSB +1
to clock in the data. The first bit of data appears on the SDINx 8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock.
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
MSB
MSB -1
MSB -2
LSB +2
LSB +1
LSB
Figure 6. Right-Justified Timing Diagram
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AD1833
AUX-Mode Timing--Interfacing to a SHARC (R)
In AUX mode, the AD1833 is the master and generates a frame sync signal (FSTDM) on its L/RCLK pin, and a bit clock (BCLKTDM) on its BCLK pin, both of which are used to control the data transmission from the SHARC. The bit clock runs at a frequency of 256 x fS. In this mode all data is written on the rising edge of the bit clock and read on the falling edge of the bit clock. The AD1833 starts the frame by raising a frame sync on the rising edge of bit clock. The SHARC recognizes this on the following falling edge of bit clock, and is ready to start outputting data on the next rising edge of bit clock. Each channel is given a 32-bit clock slot, the data is left justified and uses 16, 20, or 24 of the 32 bits. An enlarged diagram (see Figure 6) is provided detailing this. The data is sent from the SHARC to the AD1833 on the SDIN1 pin and is provided in the following order, MSB first--Internal DACL0, Internal DACL1, Internal DACL2, AUX DACL0, Internal DACR0, Internal DACR1, Internal DACR2 and AUX DACR0. The data is written on the rising edge of bit clock and read by the AD1833 on the falling edge of bit clock. The left and right
FSTDM
data destined for the auxiliary DAC is sent to it in standard I 2S format in the next frame using the SDIN2, SDIN3, and SOUT pins as the L/RCLK, BCLK, and SDIN pins respectively for communicating with the auxiliary DAC.
DSP Mode Timing
DSP Mode Timing uses the rising edge of the frame sync signal on the L/RCLK pin to denote the start of the transmission of a data word. Note that for both left and right channels a rising edge is used; therefore in this mode there is no way to determine which data is intended for the left channel and which is intended for the right. The DSP writes data on the rising edge of BCLK and the AD1833 reads it on the falling edge. The DSP raises the frame sync signal on the rising edge of BCLK and then proceeds to transmit data, MSB first, on the next rising edge of BCLK. The data length can be 16, 20, or 24 bits. The frame sync signal can be brought low any time at or after the MSB is transmitted, but must be brought low at least one BCLK period before the start of the next channel transmission.
BCLKTDM
INTERNAL DAC L0
INTERNAL DAC L1
INTERNAL DAC L2
AUXILIARY DAC L0
INTERNAL DAC R0
INTERNAL DAC R1
INTERNAL DAC R2
AUXILIARY DAC R0
BCLKTDM
24-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +8
LSB +7
LSB +6
LSB +5
LSB +4
LSB +3
LSB +2
LSB +1
LSB
20-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +4
LSB +3
LSB +2
LSB +1
LSB
16-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB
Figure 7. Aux-Mode Timing
L/RCLK
BCLK
SDATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
MSB -5
MSB -6
MSB
MSB -1
MSB -2
MSB -3
MSB -4
MSB -5
MSB -6
MSB
32 BCLKs
32 BCLKs
Figure 8. DSP Mode Timing
SHARC is a registered trademark of Analog Devices, Inc.
REV. 0
-13-
AD1833
Packed Mode 128 Packed Mode 256
In Packed Mode 128, all six data channels are "packed" into one sample interval on one data pin. The BCLK runs at 128 x fS; therefore there are 128 BCLK periods in each sample interval. Each sample interval is broken into eight time slots, six slots of 20 BCLKs and two of four BCLKs. The data length is restricted in this mode to a maximum of 20 bits. The three left channels are written first, MSB first, and the data is written on the falling edge of BCLK. After the three left channels are written, there is a space of four BCLKs and then the three right channels are written. The L/RCLK defines the left and right data transmission; it is high for the three left channels and low for the three right channels.
In Packed Mode 256 all six data channels are "packed" into one sample interval on one data pin. The BCLK runs at 256 x fS; therefore there are 256 BCLK periods in each sample interval. Each sample interval is broken into eight time slots of 32 BCLKs each. The data length can be 16, 20, or 24 bits. The three left channels are written first, MSB first, and the data is written on the falling edge of BCLK with a one BCLK period delay from the start of the slot. After the three left channels are written, there is a space of 32 BCLKs and then the three right channels are written. The L/RCLK defines the left and right data transmission; it is low for the three left channels and high for the three right channels.
L/RCLK
BCLK
DATA
SLOT 1 LEFT 0
SLOT 2 LEFT 1
SLOT 3 LEFT 2
BLANK SLOT 4 SCLKs
SLOT 4 RIGHT 0
SLOT 5 RIGHT 1
SLOT 6 RIGHT 2
BLANK SLOT 4 SCLKs
BCLK
20-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +4
LSB +3
LSB +2
LSB +1
LSB
16-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB
Figure 9. Packed Mode 128
L/RCLK
BCLK
DATA
SLOT 1 LEFT 0
SLOT 2 LEFT 1
SLOT 3 LEFT 2
SLOT 4 RIGHT 0
SLOT 5 RIGHT 1
SLOT 6 RIGHT 2
BCLK
24-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +8
LSB +7
LSB +6
LSB +5
LSB +4
LSB +3
LSB +2
LSB +1
LSB
20-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB +4
LSB +3
LSB +2
LSB +1
LSB
16-BIT DATA
MSB
MSB -1
MSB -2
MSB -3
MSB -4
LSB
Figure 10. Packed Mode 256
-14-
REV. 0
AD1833
0
5.62k VOUT- 5.62k 2.80k 560pF NPO 560pF NPO VOUT+ 2.80k 5.62k 5.62k
150pF NPO
-20
-40
6 OP275 5 7 604 49.9k 2.2nF NPO
dBR
-80 -100 -120 -140 0 20 40 60 kHz 80 100 120
VFILTOUT
-60
150pF NPO
Figure 11. Suggested Output Filter Schematic
Figure 14. Dynamic Range for 37 kHz @ -60 dBFS, 110 dB, Triangular Dithered Input
0 -20
0 -20
-40
-40
-60
-60
dBR
-80 -100
dBR
-80 -100 -120 -140 0 2 4 6 8 10 kHz 12 14 16 18 20 -120 -140
0
20
40
60 kHz
80
100
120
Figure 12. Dynamic Range for 1 kHz @ -60 dBFS, 110 dB, Triangular Dithered Input
Figure 15. Input 0 dBFS @ 37 kHz, BW 20 Hz to 120 kHz, SR 96 kHz, THD + N -95 dBFS
0 -20
0 -20 -40 -60
-40
-60
dBR
dBV
-80 -100
-80 -100
-120
-120 -140 0 2 4 6 8 10 kHz 12 14 16 18 20
-140 -160
0
2
4
6
8
10 kHz
12
14
16
18
20
Figure 13. Input 0 dBFS @ 1 kHz, BW 20 Hz to 20 kHz, SR 48 kHz, THD + N -95 dBFS
Figure 16. Noise Floor for Zero Input, SR 48 kHz, SNR 110 dBFS A-Weighted
REV. 0
-15-
AD1833
-60
-20 -30
-70
-40 -50
-80
-60
dBR
dBR
-90
-70 -80
-100
-90 -100
-110
-110
-120 -100 -90
-80
-70
-60
-50 -40 dBFS
-30
-20
-10
0
-120 -100 -90
-80
-70
-60
-50 -40 dBFS
-30
-20
-10
0
Figure 17. THD + N Ratio vs. Amplitude, Input 1 kHz, SR 48 kHz, 24-Bit
Figure 18. THD + N Ratio vs. Amplitude, @ 1 kHz, SR 48 kHz
-16-
REV. 0
AD1833
DVDD -INTF 5V 10 F + 0.1 F 10 F + 0.1 F 10 F + 0.1 F 10 F + 0.1 F 10 F + 0.1 F 10 F + 0.1 F AVDD 5V
10 F + DVDD 0.1 F AVDD 10 F 0.1 F
DVDD1 9 28 DVDD2
22
7
CLATCH CDATA CCLK 26 SDATA 11 FSYNC 12 SCK 19 MCK
VA+
10nF 75RO 10nF
9
RXP
VD+
14 CLATCH 15 CDATA 16 CCLK 17 18 20 21 22 23 19 L/RCLK BCLK SDIN1 SDIN2 SDIN3 SOUT MCLK
AVDD1 AVDD2 AVDD AVDD AVDD
4 33 3 34 44
OUTLP1 OUTLN1 OUTLP2 OUTLN2 OUTLP3 OUTLN3 OUTRP1 OUTRN1 OUTRP2 OUTRN2 OUTRP3 OUTRN3 VREFX FILTDAC
1 2 47 48 45 46 36 35 38 37 40 39 42 43 + 10 F 0.1 F +
L1+ L1- L2+ L2- L3+ L3- R1+ R1- R2+ R2- R3+ R3-
10
RXN
PAL
AD1833
1k
DGND1
DGND2
GND GND
47nF
21 8
AGND DGND
CO/EO CA/E1 CB/E2 CC/F0 CD/F1 CE/F2 SEL CS12/FCK
6 5 4 3 2 27 16 13
GND GND GND GND GND
23 M0 24 20 M1 18 FILT M2 17 M3 DIR-CS8414 1 C 14 U 15 CBL 28 VERF ERF 25
29
30
5V L5 10k
0.1 F
5 6 2 4
SHLD1 SHLD1
DVDD
3
OUT U5 TORX173
SHLD1 SHLD1
Figure 19. Example Digital Interface
REV. 0
-17-
6 31 5 32 41
0.1 F
10 F
8
7
1
AD1833
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
1
0.354 (9.00) BSC SQ
48 37 36
TOP VIEW
(PINS DOWN)
0.276 (7.00) BSC SQ
25
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0 MIN
12 13 24
0.019 (0.5) BSC 7 0
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
-18-
REV. 0
-19-
-20-
C02336-2.5-4/01(0)
PRINTED IN U.S.A.

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